As is known in the art, network processors can be used to pass data traffic to various networks over different network interfaces. In general, network processors are optimized to process packets at high speeds. Network processors typically include multiple programmable packet-processing engines or elements running in parallel with mechanisms for the processing engines to communicate with each other. Network processors can include a general purpose microprocessor to handle control tasks and memory controllers to facilitate movement of packets in and out of memory. Network processors further include interface modules for one or more standardized interfaces. Additional network processor modules can include coprocessors for accelerating various functions, such as encryption and decryption. Some network processors, such as the IXP family of network processors by Intel Corporation, have multiple cores on a single die. Communication between the IXP cores is accomplished through hardware-supported queuing mechanisms implemented in the memory controller(s).
Network processors can be coupled to various types of memory, such as Static Random Access Memory (SRAM), which is relatively fast and expensive, and Dynamic Random Access Memory (DRAM), which is relatively slow, dense, and inexpensive. SRAM and DRAM accesses have different signaling requirements. Accesses to SRAM require a single signal number to indicate completion of an operation, e.g., read or write. For some processor/memory implementations, DRAM accesses require two signals to indicate completion of an operation. Only after both DRAM signals have been generated is the operation guaranteed to have finished.
As is well known in the art, microcode is used to program the processing elements of the network processor. The microcode utilizes hardware signals supported by the processor that can, for example, indicate completion of various asynchronous operations. A processor has a predetermined number of hardware signals that can be used when programming the processing elements to notify threads of specific events. Microcode must generally be written such that no one signal is used concurrently by more than one Input/Output (I/O) operation in order to guarantee code correctness. In addition, microcode is usually written such that each operation receives a statically assigned signal. While static signal allocation prevents concurrent use of a signal, the total number of possible operations available to any microcode thread is limited. On some Intel IXP network processors, for example, fifteen signals are available per thread. This limits the number of memory accesses to fifteen total SRAM operations or seven total DRAM operations (DRAM requires two signals) using static signal allocation. For example, using static signal allocation where fifteen signals are supported in hardware, it would not be possible to code two separate DRAM reads, two separate SRAM reads, two separate DRAM writes, two separate SRAM writes, and four separate SRAM dequeue operations.